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copyright ? cirrus logic, inc. 2005 (all rights reserved) http://www.cirrus.com 120 db, 192 khz multi-bit dac with volume control features ? advanced multi-bit delta-sigma architecture ? 120 db dynamic range ? -107 db thd+n ? low clock jitter sensitivity ? differential analog outputs ? pcm input ? 102 db of stopband attenuation ? supports sample rates up to 192 khz ? accepts up to 24 bit audio data ? supports all industry standard audio interface formats ? selectable digital filter response ? volume control with 1/2 db step size and soft ramp ? flexible channel routing and mixing ? selectable de-emphasis ? supports stand-alone or i2c/spi ? configuration embedded level translators ? 1.8 v to 5 v serial audio input ? 1.8 v to 5 v control data input ? direct stream digital (dsd) ? dedicated dsd input pins ? on-chip 50 khz filter to meet scarlet book sacd recommendations ? matched pcm and dsd analog output levels ? non-decimating volume control with 1/2 db step size and soft ramp ? dsd mute detection ? supports phase-modulated inputs ? optional direct dsd path to on-chip switched capacitor filter ? control output for external muting ? independent left and right mute controls ? supports auto detection of mute output polarity ? typical applications ? dvd players ? sacd players ? a/v receivers ? professional audio products pcm serial interface multibit ? modulator interpolation filter with volume control internal voltage reference external mute control switched capacitor dac and filter dsd interface pcm input left and right mute controls right differential output left differential output dsd input dsd processor 1.8 v to 5v 1.8 v to 5 v -volume control -50khz filter switched capacitor dac and filter mux direct dsd level translator level translator hardware or i 2 c/spi control data mux multibit ? modulator interpolation filter with volume control mux mux 3.3 v to 5 v 5 v register/hardware configuration july '05 ds568f1 CS4398
2 ds568f1 CS4398 stand-alone mode features ? selectable oversampling modes ? 32 khz to 54 khz sampling rates ? 50 khz to 108 khz sampling rates ? 100 khz to 216 khz sampling rates ? selectable serial audio interface formats ? left-justified, up to 24 bit ? i2s, up to 24 bit ? right-justified 16 bit ? right-justified 24 bit ? auto mute output polarity detect ? auto mute on static pcm samples ? 44.1 khz 50/15 s de-emphasis available ? soft volume ramp-up after reset is released control port mode features ? selectable oversampling modes ? 32 khz to 54 khz sampling rates ? 50 khz to 108 khz sampling rates ? 100 khz to 216 khz sampling rates ? selectable serial audio interface formats ? left-justified, up to 24 bit ? i2s, up to 24 bit ? right-justified 16 bit ? right-justified 18 bit ? right-justified 20 bit ? right-justified 24 bit ? direct stream digital mode ? selectable auto or manual mute polarity ? selectable interpolation filters ? selectable 32, 44.1, and 48 khz de-emphasis ? configurable atapi mixing functions ? configurable volume and muting controls description the CS4398 is a complete stereo 24 bit/192 khz digital- to-analog system. this d/a system includes digital de- emphasis, half db step size volume control, atapi channel mixing, selectable fast and slow digital interpo- lation filters followed by an oversampled multi-bit delta- sigma modulator that includes mismatch shaping tech- nology that eliminates distortion due to capacitor mismatch. following this stage is a multi-element switched capacitor stage and lo w pass filter with differ- ential analog outputs. the CS4398 also has an proprietary dsd processor that allows for volume control and 50 khz on-chip filter- ing without an intermediate decimation stage. it also offers an optional path for direct dsd conversion by di- rectly using the multi-element switched capacitor array. the CS4398 accepts pcm data at sample rates from 32 khz to 216 khz, dsd audio data, has selectable dig- ital filters, consumes little power, and delivers excellent sound quality. ordering information product description package pb-free grade temp range container order # CS4398 120 db, 192 khz multi- bit dac with volume control 28-pin tssop yes commercial -10 to +70 c rail CS4398-czz tape & reel CS4398-czzr cdb4398 CS4398 evaluation board - - - - cdb4398
ds568f1 3 CS4398 table of contents 1. pinout drawing ........................................................................................................... ...... 6 2. characteristics and specifications ........................................................................ 8 specified operating conditions . .............. ................ ............. ............. ............. ........... 8 absolute maximum ratings ...... ................ ................ ................ ............. ............. ........... 8 analog characteristics................................................................................................ 9 combined interpolation & on-chip analog filter response ........................ 10 combined interpolation & on-chip analog filter response ........................ 11 dsd combined digital and on-chip anal og filter response. ................ ......... 11 switching characteristics ........................................................................................ 12 switching characteristics - dsd ............................................................................. 14 switching characteristics - control po rt - i2c format ................................ 15 switching characteristics - control po rt - spi? format............................ 16 dc electrical characteristics ............................................................................... 17 digital interface specifications ............................................................................. 18 3. typical connection diagram .................................................................................. 19 4. applications .............................................................................................................. ....... 20 4.1 grounding and power supply decoupling .... ................................................................... 20 4.2 analog output and filtering ............................................................................................. 20 4.3 the mutec outputs ....................................................................................................... 20 4.4 oversampling modes ....................................................................................................... 2 1 4.5 master and serial clock ratios ............. .......................................................................... 21 4.6 stand-alone mode settings ............................................................................................. 22 4.7 control port mode ......................................................................................................... .. 23 5. control port interface ............................................................................................. 25 5.1 memory address pointer (m ap) ...................................................................................... 25 5.2 enabling the control port ................................................................................................ 2 5 5.3 format selection .......................................................................................................... ... 25 5.4 i2c format ................................................................................................................ ....... 25 5.5 spi format ................................................................................................................ ...... 26 7.1 chip id - register 01h .................................................................................................... .29 7.2 mode control 1 - register 02h ........................................................................................ 29 7.3 volume mixing and inversion control - register 03h ...................................................... 30 7.4 mute control - register 04h ............................................................................................ 33 7.5 channel a volume control - register 05h . ...................................................................... 34 7.6 channel b volume control - register 06h . ...................................................................... 34 7.7 ramp and filter control - register 07h . .......................................................................... 35 7.8 misc. control - register 08h ............................................................................................ 37 7.9 misc. control - register 09h ............................................................................................ 38 8. parameter definitions .................................................................................................. 39 9. references ................................................................................................................ ........ 39 10. package dimensions .................................................................................................... 40 10.1 28-tssop ................................................................................................................. .... 40 thermal characteristics and specificatio ns ................ ............. ............. ......... 40 11. appendix ............. ................ ................ ................. ................ ................ .............. ........... 41
4 ds568f1 CS4398 list of figures figure 1. pinout drawing....................................................................................................... .......... 6 figure 2. serial mode input timing ............................................................................................. .. 12 figure 3. format 0 - left-justifie d up to 24-bit data ..................................................................... 13 figure 4. format 1 - i2s up to 24-bit data ..................................................................................... 13 figure 5. format 2, right-justified 16-bit data. format 3, right-justified 24-bit data. format 4, right-justified 20-bit data . (available in control port mode only) format 5, right-justified 18-bit data. (avail able in control port mode only) ................ 13 figure 6. direct stream digital - serial audio in put timing........................................................... 14 figure 7. direct stream digital - serial audio in put timing for phase modulation mode.............. 14 figure 8. control port timing - i2c format.......... .......................................................................... 1 5 figure 9. control port timing - spi format (rea d/write) ............................................................. 16 figure 10. typical connection diagram.............. .......................................................................... 19 figure 11. recommended output filter........................................................................................ 20 figure 12. recommended mute circuitry ..................................................................................... 21 figure 13. dsd phase modulation mode diagram ....................................................................... 24 figure 14. control port timing, i2c format................................................................................... 26 figure 15. control port timing, spi format (write) ...................................................................... 27 figure 16. control port timing, spi format (read)...................................................................... 27 figure 17. de-emphasis curve................................................................................................... .. 30 figure 18. atapi block diagram ................................................................................................. .31 figure 19. 28l tssop (4.4 mm body) package dra wing ............................................................ 40 figure 20. single-speed (fast) stopband rejection...................................................................... 41 figure 21. single-speed (fast) transition band ............................................................................ 41 figure 22. single-speed (fast) transition band (detail) ................................................................ 41 figure 23. single-speed (fast) passband ripple .......................................................................... 41 figure 24. single-speed (slow) stopband rejection .................................................................... 41 figure 25. single-speed (slow) transition band........................................................................... 41 figure 26. single-speed (slow) transition band (detail)............................................................... 42 figure 27. single-speed (slow) passband ripple......................................................................... 42 figure 28. double-speed (fast) stopband rejection .................................................................... 42 figure 29. double-speed (fast) transition band. .......................................................................... 42 figure 30. double-speed (fast) tr ansition band (detail)............................................................... 42 figure 31. double-speed (fast) passband ripple......................................................................... 42 figure 32. double-speed (slow) stopband rejection ................................................................... 43 figure 33. double-speed (slow) transition band ......................................................................... 43 figure 34. double-speed (slow) transition band (detail) ............................................................. 43 figure 35. double-speed (slow) passband ripple ....................................................................... 43 figure 36. quad-speed (fast) st opband rejection ....................................................................... 43 figure 37. quad-speed (fast) transition band ... .......................................................................... 43 figure 38. quad-speed (fast) tr ansition band (detail) ................................................................. 44 figure 39. quad-speed (fast) passband ripple ..... ...................................................................... 44 figure 40. quad-speed (slow) stopband rejection...................................................................... 44 figure 41. quad-speed (slow) transition band.. .......................................................................... 44 figure 42. quad-speed (slow) transition band (detail)................................................................ 44 figure 43. quad-speed (slow) passband ripple.... ...................................................................... 44
ds568f1 5 CS4398 list of tables table 1. clock ratios .......................................................................................................... .......... 21 table 2. common clock frequencies........................................................................................... 22 table 3. digital interface forma t, stand-alone mode options...................................................... 22 table 4. mode selection, stand-alone mode options .................................................................. 22 table 5. digital interface formats - pcm mode.. .......................................................................... 29 table 6. digital interface form ats - dsd mode ............................................................................ 30 table 7. example digital volume settings .......... .......................................................................... 34 table 8. revision table ........................................................................................................ ........ 45
6 ds568f1 CS4398 1. pinout drawing figure 1. pinout drawing dsd_b dsd_a dsd_sclk vls sdin vq sclk amutec lrck aouta- mclk aouta+ vd va dgnd agnd m3 (ad1/cdin) aoutb+ m2 (scl/cclk) aoutb- m1 (sda/cdout) bmutec m0 (ad0/cs )vref rst ref_gnd vlc filt+ 1 2 3 4 5 6 7 821 22 23 24 25 26 27 28 9 10 11 12 17 18 19 20 13 14 15 16
ds568f1 7 CS4398 pin name pin # pin description dsd_a dsd_b 28 1 direct stream digital input ( input ) - input for direct stream digital serial audio data. dsd_sclk 2 dsd serial clock ( input ) - serial clock for the direct stream digital audio interface. sdin 3 serial audio data input ( input ) - input for two?s complement serial audio data. sclk 4 serial clock ( input ) - serial clock for the serial audio interface. lrck 5 left right clock ( input ) - determines which channel, left or right, is currently active on the serial audio data line. mclk 6 master clock ( input ) - clock source for the delta-sigma modulator and digital filters. vd 7 digital power ( input ) - positive power for the digital section. dgnd 8 digital ground ( input ) - ground reference for the digital section. rst 13 reset ( input ) - the device enters system reset when enabled. vlc 14 control port power ( input ) - positive power for control port i/o. filt+ 15 positive voltage reference ( output ) - positive reference voltage for the internal sam- pling circuits. ref_gnd 16 reference ground ( input ) - ground reference for the internal sampling circuits. vref 17 voltage reference ( input ) - positive voltage reference for the internal sampling circuits. bmutec amutec 18 25 mute control ( output ) - the mute control pin is active during power-up in itialization, mut- ing, power-down or if the master clock to left/r ight clock frequency ratio is incorrect. during reset, these outputs are set to a high impedance. aoutb+ aoutb- 20 19 differential right channel analog output ( output ) - the full-scale differential analog output level is specified in the analog characteristics specification table. agnd 21 analog ground ( input ) - ground reference for the analog section. va 22 analog power ( input ) - positive power for the analog section. aouta+ aouta- 23 24 differential left channel analog output ( output ) - the full-scale differential analog out- put level is specified in the analog characteristics specification table. vq 26 quiescent voltage ( output ) - filter connection for internal quiescent voltage. vls 27 serial audio interface power ( input ) - positive power for serial audio interface i/o. stand-alone mode definitions m3 m2 m1 m0 9 10 11 12 mode selection ( input ) - determines the operational mode of the device. control port mode definitions ad1/cdin 9 address bit 1 (i2c) / control data input (spi) ( input ) - ad1 is a chip address pin in i2c mode; cdin is the input data line for th e control port interface in spi mode. scl/cclk 10 serial contro l port clock ( input ) - serial clock for the serial control port. sda/cdout 11 serial control data (i2c) / control data output (spi) ( input/output ) - sda is a data i/o line in i2c mode. cdout is the output data li ne for the control port interface in spi mode. ad0/cs 12 address bit 0 (i2c) / contro l port chip select (spi) ( input ) - ad0 is a chip address pin in i2c mode; cs is the chip select signal for spi format.
8 ds568f1 CS4398 2. characteristics a nd specifications (min/max performance characteristics and specifications are guaranteed over the specified operating conditions. typical performance characte ristics are derived from measurements taken at t a =25 c, va = 5.0 v, vd = 3.3 v.) specified operating conditions (agnd = 0 v; all voltages with respect to ground.) absolute maximum ratings (agnd = 0 v; all voltages with respect to ground.) warning: operation at or beyond these limit s may result in permanent damage to the device. normal operation is not guaranteed at these extremes. parameters symbol min typ max units dc power supply analog power voltage reference digital power serial audio interface power control port interface power va vref vd vls vlc 4.75 4.75 3.1 1.7 1.7 5.0 5.0 3.3 3.3 3.3 5.25 5.25 5.25 5.25 5.25 v v v v v specified temperature range -cz & -czz t a -10 - 70 c parameters symbol min max units dc power supply analog power voltage reference digital power serial audio interface power control port interface power va vref vd vls vlc -0.3 -0.3 -0.3 -0.3 -0.3 6.0 6.0 6.0 6.0 6.0 v v v v v input current any pin except supplies i in -10ma digital input voltage serial audio interface control port interface v in-ls v in-lc -0.3 -0.3 vls+ 0.4 vlc+ 0.4 v v ambient operating temperature (power applied) t a -55 125 c storage temperature t stg -65 150 c
ds568f1 9 CS4398 analog characteristics (test conditions (unless otherwise spec ified): input test signal is a 997 hz sine wave at 0 dbfs; measurement bandwidth is 10 hz to 20 khz; test load r l = 1 k ? , c l = 10 pf.) notes: 1. one-half lsb of triangular pdf dither is added to data. 2. performance limited by 16-bit quantization noise. 3. dsd performance may be limited by the source recording. 0 db-sacd = 50% modulation index. parameter symbol min typ max unit dynamic performance - all pcm modes and dsd processor mode dynamic range (note 1) 24-bit a-weighted unweighted 16-bit a-weighted (note 2) unweighted 114 111 - - 120 117 97 94 - - - - db db db db total harmonic distortion + noise (note 1) 24-bit 0 db -20 db -60 db 16-bit 0 db (note 2) -20 db -60 db thd+n - - - - - - -107 -97 -57 -94 -74 -34 -100 - - - - - db db db db db db idle channel noise / signa l-to-noise ratio - 120 - db dynamic performanc e - direct dsd dynamic range (note 3) a-weighted unweighted 111 108 117 114 - - db db total harmonic distortion + noise (note 3) 0 db -20 db -60 db thd+n - - - -104 -94 -54 -98 - - db db db dynamic performanc e for all modes interchannel isolation (1 khz) - 110 - db dc accuracy interchannel gain mismatch icgm - 0.1 - db gain drift - 100 - ppm/c analog output characteri stics and specifications full scale differential pcm, dsd processor output voltage direct dsd mode 132%?v a 94%?v a 134%?v a 96%?v a 136%?v a 98%?v a vpp vpp output impedance z out -118- ? minimum ac-load resistance r l -1-k ? maximum load capacitance c l -100-pf
10 ds568f1 CS4398 combined interpolat ion & on-chip analog filter response the filter characteristics have been normalized to the sa mple rate (fs) and can be referenced to the desired sam- ple rate by multiplying the given characteristic by fs.) (see note 9.) 4. slow roll-off interpolation filter is only available in control port mode. 5. filter response is guaranteed by design. 6. response is clock-dependent and will scale with fs. 7. for single-speed mode, the measurement bandwidth is from stopband to 3 fs. for double-speed mode, the measurement bandwidth is from stopband to 3 fs. for quad-speed mode, the measurement bandwidth is from stopband to 1.34 fs. 8. de-emphasis is available only in single-speed mode ; only 44.1 khz de-emphasis is available in stand- alone mode. 9. amplitude vs. frequency plots of this data are available in the ?appendix? on page 41. parameter fast roll-off unit min typ max combined digital and on-chip analog filter response - single-speed mode - 48 khz (note 5) passband (note 6) to -0.01 db corner to -3 db corner 0 0 - - .454 .499 fs fs frequency response 10 hz to 20 khz -0.01 - +0.01 db stopband 0.547 - - fs stopband attenuation (note 7) 102 - - db group delay - 9.4/fs - s de-emphasis error (note 8) fs = 32 khz (relative to 1 khz) fs = 44.1 khz fs = 48 khz - - - - - - 0.23 0.14 0.09 db db db combined digital and on-chip analog filter response - double-speed mode - 96 khz (note 5) passband (note 6) to -0.01 db corner to -3 db corner 0 0 - - .430 .499 fs fs frequency response 10 hz to 20 khz -0.01 - 0.01 db stopband .583 - - fs stopband attenuation (note 7) 80 - - db group delay - 4.6/fs - s combined digital and on-chip analog filter response - quad-speed mode - 192 khz (note 5) passband (note 6) to -0.01 db corner to -3 db corner 0 0 - - .105 .490 fs fs frequency response 10 hz to 20 khz -0.01 - 0.01 db stopband .635 - - fs stopband attenuation (note 7) 90 - - db group delay - 4.7/fs - s
ds568f1 11 CS4398 combined interpolation & on-c hip analog filter response (continued) dsd combined digital and on -chip analog filter response parameter slow roll-off (note 4) unit min typ max single-speed mode - 48 khz (note 5) passband (note 6) to -0.01 db corner to -3 db corner 0 0 - - 0.417 0.499 fs fs frequency response 10 hz to 20 khz -0.01 - +0.01 db stopband .583 - - fs stopband attenuation (note 7) 64 - - db group delay - 6.65/fs - s de-emphasis error (note 8) fs = 32 khz (relative to 1 khz) fs = 44.1 khz fs = 48 khz - - - - - - 0.23 0.14 0.09 db db db double-speed mode - 96 khz (note 5) passband (note 6) to -0.01 db corner to -3 db corner 0 0 - - .296 .499 fs fs frequency response 10 hz to 20 khz -0.01 - 0.01 db stopband .792 - - fs stopband attenuation (note 7) 70 - - db group delay - 3.9/fs - s quad-speed mode - 192 khz (note 5) passband (note 6) to -0.01 db corner to -3 db corner 0 0 - - .104 .481 fs fs frequency response 10 hz to 20 khz -0.01 - 0.01 db stopband .868 - - fs stopband attenuation (note 7) 75 - - db group delay - 4.2/fs - s parameter min typ max unit dsd processor mode (note 5) passband (note 6) to -3 db corner 0 - 50 khz frequency response 10 hz to 20 khz -0.05 - 0.05 db roll-off 27 - - db/oct direct dsd mode (note 5) passband (note 6) to -0.1 db corner to -3 db corner 0 0 - - 26.9 176.4 khz khz frequency response 10 hz to 20 khz -0.1 - 0 db
12 ds568f1 CS4398 switching characteristics (inputs: logic 0 = gnd, logic 1 = vls, cl = 20 pf) parameters symbol min typ max units input sample rate single-speed mode double-speed mode quad-speed mode fs fs fs 30 50 100 - - - 54 108 216 khz khz khz mclk frequency see tables 1 & 2 (page 21) for compatible frequencies mclk duty cycle 40% - 60% lrck duty cycle 45% 50 55% sclk pulse width low t sclkl 20 - - ns sclk pulse width high t sclkh 20 - - ns sclk period single-speed mode t sclkw --ns double-speed mode t sclkw --ns quad-speed mode t sclkw --ns sclk rising to lrck edge delay t slrd 20 - - ns sclk rising to lrck edge setup time t slrs 20 - - ns sdata valid to sclk rising setup time t sdlrs 22 - - ns sclk rising to sdata hold time t sdh 20 - - ns sclkh t slrs t slrd t sdlrs t sdh t sclkl t sdata sclk lrck figure 2. serial mode input timing 1 128 () fs -------------------- - 1 64 () fs ----------------- - 2 mclk ---------------- -
ds568f1 13 CS4398 lrck sclk left channel right channel sdata +3 +2 +1 lsb +5 +4 msb -1 -2 -3 -4 -5 +3 +2 +1 lsb +5 +4 msb -1 -2 -3 -4 figure 3. format 0 - left-jus tified up to 24-bit data lrck sclk left channel right channel sdata +3 +2 +1 lsb +5 +4 msb -1 -2 -3 -4 -5 +3 +2 +1 lsb +5 +4 msb -1 -2 -3 -4 figure 4. format 1 - i2s up to 24-bit data lrck sclk left channel sdata +5 +4 +3 +2 +1 lsb msb -1 -2 -3 -4 -5 32 clocks right channel lsb +5 +4 +3 +2 +1 lsb msb -1 -2 -3 -4 -5 +6 -6 +6 -6 figure 5. format 2, ri ght-justified 16-bit data. format 3, right-justi fied 24-bit data. format 4, right-justified 20-bit data. (available in control port mode only) format 5, right-justified 18-bit data. (available in control port mode only)
14 ds568f1 CS4398 switching characteristics - dsd (logic 0 = agnd = dgnd; logic 1 = vls volts; c l =20pf) parameter symbol min typ max unit mclk duty cycle 40 - 60 % dsd_sclk pulse width low t sclkl 160 - - ns dsd_sclk pulse width high t sclkh 160 - - ns dsd_sclk frequency (64x oversampled) (128x oversampled) 1.024 2.048 - - 3.2 6.4 mhz mhz dsd_a / _b valid to dsd_sclk rising setup time t sdlrs 20 - - ns dsd_sclk rising to dsd_a or dsd_b hold time t sdh 20 - - ns dsd clock to data transition (phase modulation mode) t dpm -20 - 20 ns sclkh t sclkl t dsd_a , dsd_b dsd_sclk sdlrs t sdh t figure 6. direct stream digital - serial audio input timing dpm t dsd_a, dsd_b dsd_sclk (64fs) dsd_sclk (128fs) dpm t figure 7. direct stream digital - serial audio input timing for phase modulation mode
ds568f1 15 CS4398 switching characteristics - control port - i2c format (inputs: logic 0 = gnd, logic 1 = vlc, c l =20pf) 10. data must be held for sufficient ti me to bridge the transition time, t fc , of scl. parameter symbol min max unit scl clock frequency f scl - 100 khz rst rising edge to start t irs 500 - ns bus free-time between transmissions t buf 4.7 - s start condition hold time (p rior to first clock pulse) t hdst 4.0 - s clock low time t low 4.7 - s clock high time t high 4.0 - s setup time for repeated start condition t sust 4.7 - s sda hold time from scl falling (note 10) t hdd 0-s sda setup time to scl rising t sud 250 - ns rise time of scl and sda t rc , t rd -1s fall time scl and sda t fc , t fd -300ns setup time for stop condition t susp 4.7 - s acknowledge delay from scl falling t ack 300 1000 ns t buf t hdst t low t hdd t high t sud stop s tart sda scl t irs rst t hdst t rc t fc t sust t susp start stop repeated t rd t fd t ack figure 8. control port timing - i2c format
16 ds568f1 CS4398 switching characteristics - control port - spi ? format (inputs: logic 0 = gnd, logic 1 = vlc, c l =20pf) 11. t spi only needed before first falling edge of cs after rst rising edge. t spi = 0 at all other times. 12. data must be held for sufficient time to bridge the transition time of cclk. 13. for f sck < 1 mhz. 14. cdout should not be sampled during this time period. 15. this time is by design and not tested. parameter symbol min max unit cclk clock frequency f sclk -6mhz rst rising edge to cs falling t srs 500 - ns cclk edge to cs falling (note 11) t spi 500 - ns cs high time between transmissions t csh 1.0 - s cs falling to cclk edge t css 20 - ns cclk low time t scl 66 - ns cclk high time t sch 66 - ns cdin to cclk rising setup time t dsu 40 - ns cclk rising to data hold time (note 12) t dh 15 - ns rise time of cclk and cdin (note 13) t r2 -100ns fall time of cclk and cdin (note 13) t f2 -100ns transition time from cclk to cdout valid (note 14) t scdov -40ns time from cs rising to cdout high-z (note 15) t cscdo -20ns t r2 t f2 t dsu t dh t sch t scl cs cclk cdin t css t csh t spi t srs rst cdout t scdov t scdov t cscdo hi-impedance figure 9. control port timing - spi format (read/write)
ds568f1 17 CS4398 dc electrical characteristics 16. normal operation is defined as rs t pin = high with a 997 hz, 0 dbfs input sampled at the highest fs for each speed mode, and open outputs, unless otherwise specified. 17. i a measured with no loading on the amutec and bmutec pins. 18. i lc measured with no external loading on pin 11 (sda). 19. power-down mode is defined as rst pin = low with all clock an d data lines held static. 20. valid with the recommended capacitor values on filt+ and v q as shown in the ?typical connection dia- gram? on page 19. 21. this current is sourced/sinked directly from the va supply. parameters symbol min typ max units normal operation (note 16) power supply current v a = 5 v (note 17) v ref = 5 v v d = 5 v v d = 3.3 v interface current (note 18) i a i ref i d i d i lc i ls - - - - - - 25 1.5 25 18 2 80 28 2 38 27 - - ma ma ma ma a a power dissipation va = 5 v, vd = 5 v va = 5 v, vd = 3.3 v - - 258 192 340 240 mw mw power-down mode (note 19) power supply current i pd -200- a power dissipation va = 5 v, vd = 5 v va = 5 v, vd = 3.3 v - - 1 1 - - mw mw all modes of operation power supply rejection ratio (note 20) (1 khz) (60 hz) psrr - - 60 40 - - db db common mode voltage v q - 0.5?v a -v max current draw from vq i qmax -1- a filt+ nominal voltage - 0.93?v a -v maximum mutec drive current (note 21) - 3 - ma mutec high-level output voltage v oh va v mutec low-level output voltage v ol 0v
18 ds568f1 CS4398 digital interface specifications parameters symbol min typ max units input leakage current i in --10 a input capacitance - 8 - pf high-level input voltage serial i/o control i/o v ih v ih 70% 70% - - - - v ls v lc low-level input voltage serial i/o control i/o v il v il - - - - 30% 30% v ls v lc high-level output voltage (i oh = -1.2 ma) control i/o v oh 80% - - v lc low-level output voltage (i ol = 1.2 ma) control i/o v ol --20%v lc mutec auto detect input high voltage 70% va mutec auto detect input low voltage 30% va
ds568f1 19 CS4398 3. typical connec tion diagram figure 10. typical connection diagram dgnd agnd ref_gnd filt+ vq vd va vls vlc mclk sclk lrck sdin dsd_sclk dsd_a dsd_b m0 (ad0/cs) m1 (sda/cdout) m2 (scl/cclk) m3 (ad1/cdin) amutec aouta+ aouta - bmutec aoutb+ aoutb - rst vref left channel analog conditioning and mute right channel analog conditioning and mute pcm digital audio source dsd audio source controler or stand alone pull-ups/ downs va 0.1 uf 0.1 uf 100 uf 33 uf 3.3 uf 0.1 uf 0.1 uf 10 uf 10 uf 0.1 uf 0.1 uf system clock +3.3v to +5v +5v +1.8v to +5v +1.8v to +5v CS4398
20 ds568f1 CS4398 4. applications 4.1 grounding and power supply decoupling as with any high resolution converter, the CS4398 requ ires careful attention to power supply and grounding arrangements to optimize performance. the typi cal connection diagram shows the recommended power arrangement with va, vd, vls and vlc connected to cl ean supplies. decoupling capacitors should be lo- cated as close to the device package as possible. if desired, all supply pins ma y be connected to the same supply, but the recommended decoup ling capacitors should still be plac ed on each supply pin. the agnd and dgnd pins should be tied to gether with solid ground pl ane fill underneat h the converter extending out to the gnd side of the decoupling caps for va, vd , vref, and filt+. this recommended layout can be seen in the cdb4398 evaluation board and datasheet. 4.2 analog output and filtering the cirrus logic application note ?design notes for a 2- pole filter with differentia l input? (an48) discusses the second-order butterworth filter and differential to single-ended converter topology that was implemented on the CS4398 evaluation board, cdb4398, as seen in figure 11. the CS4398 does not include phase or amplitude compensa tion for an external filter. therefore, the dac system phase and amplitude response is depend ent on the external analog circuitry. figure 11. recommended output filter 4.3 the mutec outputs the amutec and bmutec pins have an auto-polarity detect feature. the mute c output pins are high impedance at the time of reset. the external mute circ uitry needs to be self-biased into an active state in order to be muted during reset. upon release of re set, the CS4398 detects the status of the mutec pins (high or low) and then selects that state as the polari ty to drive when the mutes become active. the external- bias voltage level that the mutec pins see at the ti me of release of reset must meet the ?mutec auto de- tect input high/low voltage? specifications as ou tlined in the digital char acteristics in section 2. figure 12 shows a single example of both an active-high and an active-low mute drive circuit. in these de- signs, the pull-up and pull-down resistors have been spec ifically chosen to meet the input high/low threshold when used with the mmun2111 and mmun22 11 internal bias resistances of 10 k ? .
ds568f1 21 CS4398 use of the mute control function is not mandatory but recommended for designs requiring the absolute min- imum in extraneous clicks and pops. also, use of th e mute control function can enable the system designer to achieve idle channel noise/signal-to-noise ratios wh ich are only limited by the external mute circuit. figure 12. recommended mute circuitry 4.4 oversampling modes the CS4398 operates in one of three oversampling modes based on the input sample rate. single-speed mode supports input sample rates up to 50 khz an d uses a 128x oversampling ratio. double-speed mode supports input sample rates up to 100 khz and us es an oversampling ratio of 64x. quad-speed mode sup- ports input sample rates up to 200 khz and uses an oversampling ratio of 32x. 4.5 master and serial clock ratios the required mclk-to-lrck ratio and suggested sclk-t o-lrck ratio are outlined in table 1. mclk can be at any phase in regards to lrck and sclk. sclk, lrck and sdata must meet the phase and timing relationships outlined in section 2. some common mclk frequencies have been outlined in table 2. mclk/lrck sclk/lrck lrck single-speed 256, 384, 512, 768*, 1024*, 1152* 32, 48, 64, 96, 128 fs double-speed 128, 192, 256, 384, 512* 32, 48, 64 fs quad-speed 64 32 (16 bits only) fs 96 32, 48 fs 128, 256* 32, 64 fs 192 32, 48, 64, 96 fs *these modes are only available in control port mode by setting the appropriate mclkdiv bit. table 1. clock ratios
22 ds568f1 CS4398 table 2. common clock frequencies 4.6 stand- alone mode settings in stand-alone mode (also referred to as ?hardware mode?) the device is configured using the m0 through m3 pins. these pins must be connected to either th e vlc supply or ground. the interface format is set by pins m0 and m1. the sample rate range/oversamp ling mode (single/double/quad-speed mode) and de- emphasis are set by pins m2 and m3. the settings can be found in tables 3 and 4. table 3. digital interface forma t, stand-alone mode options table 4. mode selection, stand-alone mode options the following features are always enabled in stand- alone mode: auto-mute on zero data, auto mutec po- larity detect, ramp volume from mute to 0db by 1/8th db steps every lrck (soft ramp) after reset or clock mode change, and the fast roll-off interpolation filter is used. the following features are not available in stand-alone mode: dsd mode, right-justified 20- and 18-bit se- rial audio interfaces, mclk divide-by -2 and mclk divide-by-3 (allows 1024 and 1152 clock ratios), slow roll- off interpolation filter, volume cont rol, atapi mixing, 48 khz and 32 khz de-emphasis, and all other features enabled by registers that are not mentioned above. mode (sample- rate range) sample rate (khz) mclk (mhz) mclkdiv2 mclkdiv3 mclk ratio 256x 384x 512x 768x 1024x 1152x single-speed (32to50khz) 32 8.1920 12.2880 16.3840 24.5760 32.7680 36.8640 44.1 11.2896 16.9344 22.5792 33.8688 45.1584 - 48 12.2880 18.4320 24.5760 36.8640 49.1520 - mclk ratio 128x 192x 256x 384x 512x - double-speed (50 to 100 khz) 64 8.1920 12.2880 16.3840 24.5760 32.7680 - 88.2 11.2896 16.9344 22.5792 33.8688 45.1584 - 96 12.2880 18.4320 24.5760 36.8640 49.1520 - mclk ratio 64x* 96x 128x 192x 256x - quad-speed (100 to 200 khz) 176.4 11.2896* 16.9344 22.5792 33.8688 45.1584 - 192 12.2880* 18.4320 24.5760 36.8640 49.1520 - these modes are only available in control port mode by setting the appropriate mclkdiv bit. * this mclk ratio limits the audio word length to 16 bits; see table 1 on page 21 m1 m0 description format figure 00 left-justified, up to 24-bit data 03 01 i2s, up to 24-bit data 14 10 right-justified, 16-bit data 25 11 right-justified, 24-bit data 35 m3 m2 description 00 single-speed without de-emphasis (32 to 50 khz sample rates) 01 single-speed with 44.1 khz de-emphasis; see figure 17 on page 30 10 double-speed (50 to 100 khz sample rates) 11 quad-speed (100 to 200 khz sample rates)
ds568f1 23 CS4398 4.6.1 recommended power- up se quence (stand-alone mode) 1. hold rst low until the power supply, master, and left/right clocks are stable. in th is state, the control port is reset to its default settings. 2. bring rst high. the device will remain in a low power state and will in itiate the sta nd-alone power- up sequence following approximately 2 18 mclk cycles. 4.7 control port mode 4.7.1 recommended power- up seque nce (control port mode) 1. hold rst low until the power supply, master, and left/right clocks are stable. in th is state, the control port is reset to its default settings. 2. bring rst high. set the cpen bit (reg. 8h) prior to th e completion of the stand-alone power-up se- quence (approximately 2 18 mclk cycles). setting this bit ha lts the stand-alone power-up sequence and initializes the control port to its default setti ngs. the desired register settings can be loaded while keeping the pdn bit (reg. 8h) set to 1. 3. clear the pdn bit to initiate the power-up sequence. if the cpen bit is not written withi n the allotted time, the de vice will start-up in stan d-alone mode and begin converting data according to the current state of the m0 to m3 pins. since these pins are also the control port pins an undesired mode may be entered. for this re ason, if the cpen bit is not set before the allotted time elapses, the sdin line must be kept at static 0 (not dithered) until the device is properly configured. this will keep the device from converting da ta improperly. 4.7.2 sample rate range/oversampl ing mode (control port mode) sample rate mode selection is determined by the fm bits (reg. 02h). 4.7.3 serial audio interface formats (control port mode) the desired serial audio interface format is selected using the dif2:0 bits (reg. 02h). 4.7.4 mutec pins (c ontrol port mode) the auto-mute polarity feature (mentioned in section 4.3) is defeatable. the mutep1:0 bits in register 04h give the option to override the mute polarity wh ich was auto detected at star tup (see the register de- scription section for more details). 4.7.5 interpolation filter (control port mode) to accommodate the increasingly complex requirements of digital audio systems, the CS4398 incorpo- rates selectable interpolation filters. a fast and a slow roll-off filter are available in each of single-, double- , and quad-speed modes. these filters have been de signed to accommodate a va riety of musical tastes and styles. the filt_sel bit (reg. 07h) is used to sele ct which filter is used (s ee the register description section for more details). filter specifications can be found in section 2, and f ilter response plots can be found in figures 20 to 43 in the ?appendix? on page 41.
24 ds568f1 CS4398 4.7.6 direct stream digital (dsd ) mode (control port mode) in control port mode, the fm bits (reg. 02h) are used to configure the device for dsd mode. the dif bits (reg 02h) then control the expected dsd rate and mclk ratio. the dsd_src bit (reg. 02h) selects the input pins for dsd clocks and data. during dsd operation, the pcm-related pins should either be tied low or remain active with clocks. when the dsd related pins are not being used, they should either be tied low or remain active with clocks. the dir_dsd bit (reg 07h) selects between two proprietary methods for dsd-to-analog conversion. the first method uses a decimation-free dsd processing te chnique that allows for features such as matched pcm level output, dsd volume control, and 50 khz on -chip filter. the second method sends the dsd data directly to the on-chip switched-c apacitor filter for conversion (without the above mentioned features). the dsd_pm_en bit (reg. 09h) selects phase modulatio n (data plus data inverted ) as the style of data input. in this mode, the dsd_pm_mode bit selects whether a 128fs or 64x clock is used for phase mod- ulated 64x data (see figure 13). use of phase modulation mode may not directly effect the performance of the CS4398, but may lower the sensitivity to board-level routing of the dsd data signals. the CS4398 can detect errors in the dsd data that do not comply to the sacd specification. the static_dsd and invalid_dsd bits (reg. 09h) allow the CS4398 to alter the incoming invalid dsd da- ta. depending on the error, the data may either be attenuated or replaced with a muted dsd signal (the mutec pins would set according to the damute bit (reg. 04h)). more information for any of these register bits can be found in the register description section. the dsd input structure and analog outputs are designed to handle a nominal 0 db-sacd (50% modu- lation index) at full rated performance. signals of +3 db-sacd may be applied for brief periods of time; however, performance at these levels is not guar anteed. if sustained +3 db-sacd levels are required, the digital volume control should be set to -3.0 db. this same volume control register affects pcm output levels. there is no need to change the volume control setting between pcm and dsd in order to have the 0 db output levels match (both 0 dbfs and 0 d b-sacd will output at -3 db in this case). figure 13. dsd phase modulation mode diagram bcka (128fs) bckd (64fs) dsd_sclk dsd_a, dsd_b d1 d1 d1 d0 d2 d2 d0 dsd_sclk dsd_a, dsd_b bcka (64fs) dsd_sclk dsd phase modulation mode dsd normal mode
ds568f1 25 CS4398 5. control port interface the control port is used to load all the internal settings . the operation of the control port may be completely asyn- chronous with the audio sample rate. however, to avoid pote ntial interference problems, the control port pins should remain static if no operation is required. 5.1 memory address pointer (map) 5.1.1 memory address pointer (m ap) register detail 5.1.2 incr (auto map increment enable) default = ?0? 0 - disabled, the map will stay c onstant for su ccessive writes 1 - enabled, the map will auto increment after each byte is written, allowing blo ck reads or writes of suc- cessive registers 5.1.3 map3-0 (memory address pointer) default = ?0000? 5.2 enabling the control port on the CS4398, the control port pins are shared with st and-alone configuration pins. to enable the control port, the user must set the cpen bit. this is done by performing an i2c or spi write. once the control port is enabled, these pins are dedicated to control port functionality. to prevent audible artifacts, the cpen bit (see section 7) should be set prior to the completion of the stand- alone power-up sequence, approximately 2 18 mclk cycles. setting this bit halts the stand-alone power-up sequence and initializes the control port to its default settings. note, the cpen bit can be set any time after rst goes high; however, setting this bit after the stand-alone power-up sequence has completed can cause audible artifacts. 5.3 format selection the control port has two format s: spi and i2c, with the CS4398 operating as a slave device. if i2c operation is desired, ad0/cs should be tied to vlc or gnd. if the CS4398 ever detects a high-to-low transition on ad0/cs after power-up, spi format will automatically be selected. 5.4 i2c format in i2c format, sda is a bidirectional data line. data is clocked into and out of the part by the clock, scl, with a clock-to-data relationship as shown in figure 14. the receiving device should send an acknowledge (ack) after each byte received. there is no cs pin. pins ad0 and ad1 form the partial chip address and should be tied to vlc or gnd as required. the upper fi ve bits of the 7-bit address field must be 10011. 76 5 4 3210 incr reserved reserved reserved map3 map2 map1 map0 0 0 0 0 0000
26 ds568f1 CS4398 5.4.1 writing in i2c format to communicate with the CS4398, initiate a start condition of the bus (see figure 14.). next, send the chip address. the eighth bit of the address byte is the r/w bit (low for a write). the next byte is the mem- ory address pointer, map, which sele cts the register to be read or written. the map is then followed by the data to be written. to write mu ltiple registers, conti nue providing a clock and data, waiting for the CS4398 to acknowledge between each byte. to end the transaction, send a stop condition. 5.4.2 reading in i2c format to communicate with the CS4398, initiate a start condition of the bus (see figure 14.). next, send the chip address. the eighth bit of the address byte is the r/w bit (high for a read). the contents of the reg- ister pointed to by the map will be outp ut after the chip addres s. to read multiple re gisters, continue pro- viding a clock and issue an ack af ter each byte. to end the transaction, send a stop condition. 5.5 spi format in spi format, cs is the CS4398 chip select signal; cclk is t he control port bit clock; cdin is the input data line from the microcontroller; cdout is the output data line and the chip address is 1001100. cs , cclk,and cdin are all inputs, and data is clocked in on the rising edge of cclk. cdout is an output and is high-impedance when not actively outputting data. 5.5.1 writing in spi figure 15 shows the operation of the control port in spi format. to write to a register, bring cs low. the first seven bits on cdin form the chip address and mu st be 1001100. the eighth bit is a read/write indi- cator (r/w ), which must be low to write. the next eight bits form the memory address pointer (map), which is set to the address of the register that is to be updated. the next eight bits are the data that will be placed into register designated by the map. to write multiple registers, keep cs low and continue pro- viding clocks on cclk. end th e read transaction by setting cs high. sda scl 10011 ad1 r/w start ack data 1-8 ack data 1-8 ack stop note: if operation is a write, this byte contains the memory address pointer, map. note 1 ad0 figure 14. control port timing, i2c format
ds568f1 27 CS4398 figure 15. control port timing, spi fo rmat (write) 5.5.2 reading in spi figure 16 shows the operation of the control port in spi format. to read to a register, bring cs low. the first seven bits on cdin form the chip address and mu st be 1001100. the eighth bit is a read/write control (r/w ), which must be high to read. the cdout line will then output the data from the regi ster designated by the map. to read multiple registers, keep cs low and continue providing clocks on cclk. end the read transaction by setting cs high. the cdout line will go to a high-impedance state once cs goes high. figure 16. control port timing, spi format (read) map msb lsb data byte 1 byte n r/w map = memory address pointer address chip cdin cclk cs 1001100 lsb byte 1 byte n r/w address chip cdin cclk cs 1001100 msb data cdout
28 ds568f1 CS4398 6. register quick reference addr function 7 6 5 4 3 2 1 0 1h chip id part4 part3 part2 part1 part0 rev2 rev1 rev0 default 011 10-- - 2h mode control dsd_src dif2 dif1 dif0 dem1 dem0 fm1 fm0 default 000 00000 3h volume, mixing, and inversion control volb=a inverta invertb atapi4 atapi3 atapi2 atapi1 atapi0 default 000 01001 4h mute control pamute damute mutec a=b mute_a mute_b reserved mutep1 mutep0 default 110 00000 5h channel a vol- ume control vol7 vol6 vol5 vol4 vol3 vol2 vol1 vol0 default 000 00000 6h channel b vol- ume control vol7 vol6 vol5 vol4 vol3 vol2 vol1 vol0 default 000 00000 7h ramp and filter control szc1 szc0 rmp_up rmp_dn reserved filt_sel reserved dir_dsd default 101 10000 8h misc. control pdn cpen freeze mclkdiv2 mclkdiv3 reserved reserved reserved default 100 00000 9h misc. control 2 reserved reserved reserved reserved static_ dsd invalid_ dsd dsd_pm_ mode dsd_pm_ en default 000 01000
ds568f1 29 CS4398 7. register description ** all register access is r/ w unless specified otherwise** 7.1 chip id - register 01h function: this register is read-only. bits 7 through 3 are the part number id, which is 01110b (14h), and the remain- ing bits (2 through 0) are for the chip revision (rev. a = 000, rev. b = 001, ...) 7.2 mode control 1 - register 02h 7.2.1 dsd input source select (dsd_src) bit 7 function: when set to 0 (default), the dedicated ds d pins will be the active dsd inputs. when set to 1, the source fo r dsd inputs will be as follows: dsda input on sdata pin dsdb input on lrck pin dsd_sclk input on sclk pin the dedicated dsd pins must be tied low while not in use. 7.2.2 digital interface fo rmat (dif2:0) bits 6-4 function: these bits select the interface format for the seri al audio input. the functional mode bits determine whether pcm or dsd mode is selected. pcm mode: the required relationship between the left/right clock, serial clock and serial data is defined by the digital interface format, and the options are detailed in figures 3 through 5. 76543210 part4 part3 part2 part1 part0 rev2 rev1 rev0 01110 - - - 76543210 dsd_src dif2 dif1 dif0 dem1 dem0 fm1 fm0 00000000 dif2 dif1 dif0 description format figure 000 left-justified, up to 24-bit data 0 (default) 3 001 i2s, up to 24-bit data 14 010 right-justified, 16-bit data 25 011 right-justified, 24-bit data 35 100 right-justified, 20-bit data 45 101 right-justified, 18-bit data 55 110 reserved 111 reserved table 5. digital interf ace formats - pcm mode
30 ds568f1 CS4398 dsd mode: the relationship between the oversampling ratio of the dsd audio data and the required master clock to dsd data rate is defin ed by the digital interface format pins. 7.2.3 de- e mphasis control (dem1:0) bits 3-2 . default = 0 00 - no de-emphasis 01 - 44.1 khz de-emphasis 10 - 48 khz de-emphasis 11 - 32 khz de-emphasis function: selects the appropriate digital filter to maintain the stan- dard 15 s/50 s digital de-emphasis filter response at 32, 44.1 or 48 khz sample rates. (see figure 17) notes: de-emphasis is only available in single-speed mode. 7.2.4 functional mode (fm1:0) bits 1-0 default = 00 00 - single-speed mode (30 to 50 khz sample rates) 01 - double-speed mode (50 to 100 khz sample rates) 10 - quad-speed mode (100 to 200 khz sample rates) 11 - direct stream digital mode function: selects the required range of input sample rates or dsd mode. 7.3 volume mixing and inversi on control - register 03h dif2 dif1 dif0 description 0 0 0 64x oversampled dsd data with a 4x mclk to dsd data rate (default) 0 0 1 64x oversampled dsd data wit h a 6x mclk to dsd data rate 0 1 0 64x oversampled dsd data wit h a 8x mclk to dsd data rate 0 1 1 64x oversampled dsd data with a 12x mclk to dsd data rate 1 0 0 128x oversampled dsd data with a 2x mclk to dsd data rate 1 0 1 128x oversampled dsd data with a 3x mclk to dsd data rate 1 1 0 128x oversampled dsd data with a 4x mclk to dsd data rate 1 1 1 128x oversampled dsd data with a 6x mclk to dsd data rate table 6. digital interface formats - dsd mode 76543210 volb=a invert a invert b atapi4 atapi3 atapi2 atapi1 atapi0 00001001 gain db -10db 0db frequency t2 = 15 s t1=50 s f1 f2 3.183 khz 10.61 khz figure 17. de-emphasis curve
ds568f1 31 CS4398 7.3.1 channel b volume = cha nnel a volume (volb=a) bit 7 function: when set to 0 (default), the aouta and aoutb volume levels are independently controlled by the a and the b channel volume control bytes. when set to 1, the volume on both aouta and aoutb are determined by the a channel attenuation and volume control bytes, and the b channel bytes are ignored. 7.3.2 invert signal polari ty (invert_a) bit 6 function: when set to 1, this bit inverts the signal polarity of channel a. when set to 0 (default), this function is disabled. 7.3.3 invert signal polari ty (invert_b) bit 5 function: when set to 1, this bit inverts the signal polarity of channel b. when set to 0 (default), this function is disabled. 7.3.4 atapi channel mixing an d muting (atapi4:0) bits 4-0 default = 01001 - aouta=al, aoutb=br (stereo) function: the CS4398 implements the channel-mixing functions of the atapi cd-rom spec ification. refer to ta- ble and figure 18 for additional information. figure 18. atapi block diagram a channel volume control aouta aoutb left channel audio data right channel audio data b channel volume control mute mute
32 ds568f1 CS4398 atapi4 atapi3 atapi2 atapi1 atapi0 aouta aoutb 00000 mute mute 00001 mute br 00010 mute bl 00011 mute b[(l+r)/2] 00100 ar mute 00101 ar br 00110 ar bl 00111 ar b[(l+r)/2] 01000 al mute 01001 al br 01010 al bl 01011 al b[(l+r)/2] 01100 a[(l+r)/2] mute 01101 a[(l+r)/2] br 01110 a[(l+r)/2] bl 0 1 1 1 1 a[(l+r)/2] b[(l+r)/2] 10000 mute mute 10001 mute br 10010 mute bl 10011 mute [(bl+ar)/2] 10100 ar mute 10101 ar br 10110 ar bl 10111 ar [(al+br)/2] 11000 al mute 11001 al br 11010 al bl 11011 al [(al+br)/2] 11100 [(al+br)/2] mute 11101 [(al+br)/2] br 11110 [(bl+ar)/2] bl 1 1 1 1 1 [(al+br)/2] [(al+br)/2]
ds568f1 33 CS4398 7.4 mute control - register 04h 7.4.1 pcm auto- m ute (pamute) bit 7 function: when set to 1 (default), the digital-to-analog conver ter output will mute followi ng the reception of 8192 consecutive audio samples of static 0 or -1. a single sample of non- static data will release the mute. de- tection and muting is done independently for each ch annel. the quiescent voltage on the output will be retained, and the mute control pin will go active during the mute period. when set to 0, this function is disabled. 7.4.2 dsd auto- mute (damute) bit 6 function: when set to 1 (default), the digital -to-analog converter out put will mute following the reception of 256 re- peated 8-bit dsd mute patterns (as defined in the sacd specification). a single bit not fitting the repeated mu te pattern (mentioned above) will release the mute. detection and muting is done indepe ndently for each channel. the quiescent vo ltage on the output will be retained, and the mute control pin will go ac tive during the mute period. when set to 0, this function is disabled. 7.4.3 amutec = bmutec (mutec a=b) bit 5 function: when set to 0 (default) the amutec an d bmutec pins operate independently. when set to 1, the individual controls for amutec and bmutec are internally connected through an and gate prior to the output pins. therefore, the external amutec and bmutec pins will go active only when the requirements for both amutec a nd bmutec are valid. 7.4.4 a channel mute (mute_a) bit 4 b channel mute (mute_b) bit 3 function: when set to 1, the digital-to-anal og converter output will mute. the quiescent volt age on the output will be retained. the muting function is effected, similar to attenuation changes, by the soft and zero cross bits in the volume and mixing co ntrol register. the corr esponding mutec pin will go active following any ramping due to the soft and zero cross function. when set to 0 (default), this function is disabled. 76543210 pamute damute mutec a=b mute_a mute_b reserved mutep1 mutep0 11000000
34 ds568f1 CS4398 7.4.5 mute polarity and detect (mutep1:0) bits 1-0 default = 00 00 - auto polarity detect, selected from amutec pin 01 - reserved 10 - active low mute polarity 11 - active high mute polarity function: auto mute polarity detect (00) see section 4.3 on page 20 for description. active low mute polarity (10) when rst is low, the outputs are high -impedance and will need to be biased active. once reset has been released and after this bit is set, the mutec output pins will be active low polarity. active high mute polarity (11) at reset time, the ou tputs are high-impedance and will need to be biased ac tive. once reset has been released and after this bit is set, the mutec output pins will be active high polarity. 7.5 channel a volume co ntrol - register 05h 7.6 channel b volume co ntrol - register 06h 7.6.1 digital volume control (vol7:0) bits 7-0 default = 00h (0 db) function: the digital volume control register s allow independent control of the si gnal levels in 1/2 db increments from 0 to -127.5 db. volume settings are decoded as shown in table 7. the volume changes are imple- mented as dictated by the soft and zero cross bits in the power and muting control register. note that the values in the volume setting co lumn in table 7 are approximate. th e actual attenuation is determined by taking the decimal value of the volume register and multiplying by 6.02/12. 76543210 vol7 vol6 vol5 vol4 vol3 vol2 vol1 vol0 00000000 binary code decimal value volume setting 00000000 0 0 db 00000001 1 -0.5 db 00000110 6 -3.0 db 11111111 255 - 127.5 db table 7. example digital volume settings
ds568f1 35 CS4398 7.7 ramp and filter co ntrol - register 07h 7.7.1 soft ramp and zero cros s control (szc1:0) bits 7-6 default = 10 function: immediate change when immediate change is select ed, all level changes will take effect immediately in one step. zero cross zero cross enable dictates that si gnal-level changes, either by at tenuation changes or muting, will occur on a signal zero crossing to minimi ze audible artifacts. t he requested level-change will occur after a time- out period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 khz sample rate) if the signal does not encounter a zero crossing. the zero cross function is independently monitored and implemented for each channel. soft ramp pcm soft ramp allows level changes, both muting and a ttenuation, to be implemented by incrementally ramp- ing, in 1/8 db steps, from the curr ent level to the new level at a rate of 1 db per 8 left/right clock periods. soft ramp dsd soft ramp allows level changes, both muting and a ttenuation, to be implemented by incrementally ramp- ing, in 1/8 db steps, from the current level to the new level at a rate of 1 db per 512 dsd_sclk periods (1024 periods if 128x dsd_sclk is used). soft ramp and zero cross soft ramp and zero cross enable dictate that signa l-level changes, either by attenuation changes or mut- ing, will occur in 1/8 db steps and be implemen ted on a signal zero crossing. the 1/8 db level change will occur after a time-out period between 512 and 1024 sa mple periods (10.7 ms to 21.3 ms at 48 khz sample rate) if the signal does not encounter a zero crossi ng. the zero cross function is independently monitored and implemented for each channel. 76543210 szc1 szc0 rmp_up rmp_dn reserved filt_sel reserved dir_dsd 10110000 szc1 szc0 pcm descript ion dsd description 0 0 immediate change immediate change 01 zero cross 1 0 soft ramp soft ramp 1 1 soft ramp on zero crossings
36 ds568f1 CS4398 7.7.2 soft volume ramp- up af ter error (rmp_up) bit 5 function: an un-mute will be performed after ex ecuting an lrck/mclk ratio chan ge or error, and after changing the functional mode. when set to 1 (default), this un-mute is effected, si milar to attenuation changes, by the soft and zero cross bits in the volume and mixing control register. when set to 0, an immediate un-mute is performed in these instances. notes: for best results, it is recommended that this feature be used in conjunction with the rmp_dn bit. 7.7.3 soft ramp- down before filter mode change (rmp_dn) bit 4 function: if either the filt_sel or dem bi ts are changed the dac will stop co nversion for a period of time to change its filter values. this bit selects how the data is effected prior to and af ter the change of the filter values. when set to 1 (default), a mute will be performed pr ior to executing a filter mode change an d an un-mute will be performed after executing the filter mode change. this mute a nd un-mute are effected, similar to attenuation changes, by the soft and zero cross bits in the volume and mixing control register. when set to 0, an immediate mute is performed prior to executing a filter mode change. notes: for best results, it is recommended that this feature be used in conjunction with the rmp_up bit. 7.7.4 interpolation filter select (filt_sel) bit 2 function: when set to 0 (default), the interpolation filter has a fast roll off. when set to 1, the interpolation filter has a slow roll off. the specifications for each filter can be found in th e analog characteristics table, and response plots can be found in figures 20 to 43 found in the ?appendix? on page 41. 7.7.5 direct dsd conver sion (dir_dsd) bit 0 function: when set to 0 (default), dsd input data is sent to t he dsd processor for filtering and volume control func- tions. when set to 1, dsd input data is sent directly to the switched capaci tor dacs for a pure dsd conversion. in this mode, the full-scale dsd and pcm levels will not be matched (s ee section 2), th e dynamic range performance may be reduced, the volume control is inac tive, and the 50 khz low pass filter is not available (see section 2 for filter specifications).
ds568f1 37 CS4398 7.8 misc. control - register 08h 7.8.1 power down (pdn) bit 7 function: when set to 1 (default), the entire device enters a low-power state, and the co ntents of the control regis- ters is retained. the power-down bit defaults to ?1 ? on power-up and must be disabled before normal op- eration in control port mode can occur. this bit is ignored if cpen is not set. 7.8.2 control port enable (cpen) bit 6 function: this bit is set to 0 by default, allowing the devic e to power-up in stand-alone mode. control port mode can be accessed by setting this bit to 1. this allows operation of the device to be controlled by the regis- ters, and the pin definitions will conform to control port mode. 7.8.3 freeze controls (freeze) bit 5 function: when set to 1, this function allows modifications to be made to the registers without the changes taking effect until freeze is set back to 0. to make multiple changes in t he control port registers take effect simultaneously, enable the freeze bit, make all re gister changes, then disable the freeze bit. when set to 0 (default), register changes take effect immediately. 7.8.4 master clock divide-by- 2 enable (mclkdiv2) bit 4 function: when set to 1, the mclkdiv bit enables a circuit wh ich divides the externally applied mclk signal by 2 prior to all other in ternal circuitry. when set to 0 (default), mclk is unchanged. 7.8.5 master clock divide-by- 3 enable (mclkdiv3) bit 3 function: when set to 1, the mclkdiv bit enables a circuit th at divides the externally applied mclk signal by 3 prior to all other in ternal circuitry. when set to 0 (default), mclk is unchanged. 76543210 pdn cpen freeze mclkdiv2 mclkdiv3 reserved reserved reserved 10000000
38 ds568f1 CS4398 7.9 misc. control - register 09h 7.9.1 static dsd detect (static_dsd) bit 3 function: when set to 1 (default), the dsd processor checks fo r 28 consecutive zeroes or ones and, if detected, sends a mute signal to the dacs. the mutec pins will eventually go active according to the damute register. when set to 0, this function is disabled. 7.9.2 invalid dsd detect (invalid_dsd) bit 2 function: when set to 1, the dsd processor checks for greater than 24 out of 28 bits of the same value and, if de- tected, will attenuate the data sent to the dacs. th e mutec pins go active according to the damute register. when set to 0 (default), this function is disabled. 7.9.3 dsd p hase modulation mode select (dsd_pm_mode) bit 1 function: when set to 0 (default), the 128fs (bcka) clock should be input to dsd_sclk for phase modulation mode. (see figure 13 on page 24) when set to 1, the 64fs (bckd) clock should be input to dsd_sclk for phase modulation mode. 7.9.4 dsd phase modul ation mode enable (dsd_pm_en) bit 0 function: when set to 1, dsd phase modulation input mode is enabled and the dsd_pm_mode bit should be set accordingly. when set to 0 (default), this func tion is disabled (dsd normal mode). 7654 3 2 1 0 reserved reserved reserved reserved static_dsd invalid_dsd dsd_pm_mode dsd_pm_en 0000 1 0 0 0
ds568f1 39 CS4398 8. parameter definitions total harmonic distortion + noise (thd+n) thd+n is the ratio of the rms value of the signal to the rm s sum of all other spectral components over the specified bandwidth (typically 10 hz to 20 khz), including distortion components. expressed in decibels. dynamic range the ratio of the full-scale rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. dynamic range is a signal-to-noise measurement over the specified bandwidth made with a -60 dbfs signal. 60 db is then added to the resulting measurement to refer the measurement to full scale. this technique ensures that the distortion components are below the noise level and do not effect the measurement. this mea- surement technique ha s been accepted by the audio engineering society, aes17-1991 , and the electronic indus- tries association of japan, eiaj cp-307. interchannel isolation a measure of crosstalk between the left and right channel s. measured for each channel at the converter's output with all zeros to the input under test and a full-scale si gnal applied to the other ch annel. units in decibels. interchannel gain mismatch the gain difference between left and right channels. units in decibels. gain error the deviation from the nominal full-scale analog output for a full-scale digital input. gain drift the change in gain value with temperature. units in ppm/c. 9. references 1. cdb4398 evaluation board datasheet 2. ?design notes for a 2-pole filter with differe ntial input?. cirrus logi c application note an48 3. the i2c-bus specification: version 2.0? philips semiconductors, december 1998. http://www.semicondu ctors.philips.com ?
40 ds568f1 CS4398 10.package dimensions 10.1 28-tssop figure 19. 28l tssop (4.4 mm body) package drawing notes: 1. ?d? and ?e1? are reference datums and do not included mold flash or protrusions, but do include mold mis- match and are measured at the parting line, mold fl ash or protrusions shall not exceed 0.20 mm per side. 2. dimension ?b? does not include dambar protrusion/i ntrusion. allowable dambar protrusion shall be 0.13 mm total in excess of ?b? dimension at maximum material condition. dambar intrusion shall not reduce dimen- sion ?b? by more than 0.07 mm at least material condition. 3. these dimensions apply to the flat section of th e lead between 0.10 and 0.25 mm from lead tips. thermal characteristics and specifications 4. ja is specified according to jedec s pecifications for multi-layer pcbs. inches millimeters note dimmin nommax min nommax a----0.47----1.20 a1 0.002 0.004 0.006 0.05 0.10 0.15 a2 0.03150 0.035 0.04 0.80 0.90 1.00 b 0.00748 0.0096 0.012 0.19 0.245 0.30 2,3 d 0.378 bsc 0.382 bsc 0.386 bsc 9.60 bsc 9.70 bsc 9.80 bsc 1 e 0.248 0.2519 0.256 6.30 6.40 6.50 e1 0.169 0.1732 0.177 4.30 4.40 4.50 1 e -- 0.026 bsc -- -- 0.65 bsc -- l 0.020 0.024 0.029 0.50 0.60 0.75 0 4 8 0 4 8 jedec #: mo-153 controlling dimension is millimeters. parameters symbol min typ max units package thermal resistance (note 4) 28-tssop ja jc - - 37 13 - - c/watt c/watt e n 1 23 e b 2 a1 a2 a d seating plane e1 1 l side view end view top view
ds568f1 41 CS4398 11.appendix 0.4 0.5 0.6 0.7 0.8 0.9 1 ?120 ?100 ?80 ?60 ?40 ?20 0 frequency(normalized to fs) amplitude (db) 0.4 0.42 0.44 0.46 0.48 0.5 0.52 0.54 0.56 0.58 0.6 ?120 ?100 ?80 ?60 ?40 ?20 0 frequency(normalized to fs) amplitude (db) figure 20. single-speed (fast) stopband rejectio n figure 21. single-speed (fast) transition band 0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.55 ?10 ?9 ?8 ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 frequency(normalized to fs) amplitude (db) 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 ?0.02 ?0.015 ?0.01 ?0.005 0 0.005 0.01 0.015 0.02 frequency(normalized to fs) amplitude (db) figure 22. single-speed (fast) transition band (detail) figure 23. single-speed (fast) passband ripple 0.4 0.5 0.6 0.7 0.8 0.9 1 ?120 ?100 ?80 ?60 ?40 ?20 0 frequency(normalized to fs) amplitude (db) 0.4 0.42 0.44 0.46 0.48 0.5 0.52 0.54 0.56 0.58 0.6 ?120 ?100 ?80 ?60 ?40 ?20 0 frequency(normalized to fs) amplitude (db) figure 24. single-speed (slow) stopband rejection figure 25. sing le-speed (slow) transition band
42 ds568f1 CS4398 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 ?0.02 ?0.015 ?0.01 ?0.005 0 0.005 0.01 0.015 0.02 frequency(normalized to fs) amplitude (db) 0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.55 ?10 ?9 ?8 ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 frequency(normalized to fs) amplitude (db) figure 26. single-speed (slow) transition band (detail) figure 27. single-speed (slow) passband ripple 0.4 0.5 0.6 0.7 0.8 0.9 1 120 100 80 60 40 20 0 frequency(normalized to fs) amplitude (db) 0.4 0.42 0.44 0.46 0.48 0.5 0.52 0.54 0.56 0.58 0.6 120 100 80 60 40 20 0 frequency(normalized to fs) amplitude (db) figure 28. double-speed (fast) stopband rejectio n figure 29. double-speed (fast) transition band 0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.55 10 9 8 7 6 5 4 3 2 1 0 frequency(normalized to fs) amplitude (db) 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.02 0.015 0.01 0.005 0 0.005 0.01 0.015 0.02 frequency(normalized to fs) amplitude (db) figure 30. double-speed (fast) transition band (detail) figure 31. double-speed (fast) passband ripple
ds568f1 43 CS4398 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 120 100 80 60 40 20 0 frequency(normalized to fs) amplitude (db) 0.2 0.3 0.4 0.5 0.6 0.7 0.8 120 100 80 60 40 20 0 frequency(normalized to fs) amplitude (db) figure 32. double-speed (slow) stopband rejectio n figure 33. double-speed (slow) transition band 0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.55 10 9 8 7 6 5 4 3 2 1 0 frequency(normalized to fs) amplitude (db) 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.02 0.015 0.01 0.005 0 0.005 0.01 0.015 0.02 frequency(normalized to fs) amplitude (db) figure 34. double-speed (slow) transition band (d etail) figure 35. double-speed (slow) passband ripple 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 120 100 80 60 40 20 0 frequency(normalized to fs) amplitude (db) 0.2 0.3 0.4 0.5 0.6 0.7 0.8 120 100 80 60 40 20 0 frequency(normalized to fs) amplitude (db) figure 36. quad-speed (fast) stopband rejectio n figure 37. quad-speed (fast) transition band
44 ds568f1 CS4398 0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.55 10 9 8 7 6 5 4 3 2 1 0 frequency(normalized to fs) amplitude (db) 0 0.05 0.1 0.15 0.2 0.25 0.2 0.15 0.1 0.05 0 0.05 0.1 0.15 0.2 frequency(normalized to fs) amplitude (db) figure 38. quad-speed (fast) transition band (d etail) figure 39. quad-speed (fast) passband ripple 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 120 100 80 60 40 20 0 frequency(normalized to fs) amplitude (db) 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 120 100 80 60 40 20 0 frequency(normalized to fs) amplitude (db) figure 40. quad-speed (slow) stopband rejectio n figure 41. quad-speed (slow) transition band 0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.55 10 9 8 7 6 5 4 3 2 1 0 frequency(normalized to fs) amplitude (db) 0 0.02 0.04 0.06 0.08 0.1 0.12 0.02 0.015 0.01 0.005 0 0.005 0.01 0.015 0.02 frequency(normalized to fs) amplitude (db) figure 42. quad-speed (slow) transition band (det ail) figure 43. quad-speed (slow) passband ripple
ds568f1 45 CS4398 table 8. revision table release date changes a1 november 2002 initial release pp1 july 2003 -updated legal notice on page 46. -moved min/max/typ spec note from ?analog characteristics? (on page 9) to ?characteristics and specifications? on page 8. -changed heading ?recommended o perating conditions? to ?speci- fied operating condi tions? on page 8. -updated full-scale output specifications on page 9 -updated filt+ nominal voltage specification on page 17 -added control port note to table 1 on page 21 -added 64x mclk ratio note to table 2 on page 22 -changed default value of dif0 in register 02h on page 28 and -updated the definition of the ?digital volume control (vol7:0) bits 7-0? on page 34 pp2 february 2004 -updated front page block diagram -updated front page thd+n spec -added note for -czz package option -updated legal notice -corrected 768x mode in tables 1 and 2 to use mclkdiv2 -added note for 0 db-sacd to analog characteristics -updated typ and max thd+n specs -updated full-scale output levels -updated vil spec -updated voh and vol levels and conditions -updated max sample rate specs -updated recommended filt+ capacitor value in typical connection diagram -corrected atapi table values 19d and 23d pp3 september 2004 updated ds w/ lead-free device ordering info. pp4 may 2005 -removed -cz ordering option (pcn_0044 dated jan. 2005) -improved interchannel isolation specification -updated analog output impedance -corrected ramp_up and ramp_dn bit descriptions -updated legal text f1 july 2005 -changed datasheet status to final -updated legal text
46 ds568f1 CS4398 contacting cirrus logic support for all product questions and inquiries cont act a cirrus logic sales representative. to find one nearest you go to www.cirrus.com important notice cirrus logic, inc. and its subsidiaries ("cirrus") believe that the information contained in this document is accurate and reli able. however, the information is sub- ject to change without notice and is provided "as is" without wa rranty of any kind (express or implied). customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. all products a re sold subject to the terms and con- ditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limi tation of liability. no responsibility is assumed by cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. this document is the property of cirrus and by furnishing this information, cirrus gr ants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. cirrus owns t he copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization w ith respect to cirrus integrated circuits or other products of cirrus. this consent does not extend to other copying such as copying for general distribution, a dvertising or promotional purposes, or for creating any work for resale. certain applications using semiconductor products may involve potential risks of death, personal injury, or severe property or environmental damage ("crit ical applications"). cirrus products are not designed, auth orized or warrant- ed for use in aircraft systems, military applications, products surgically implanted into the body, automotive safety or security devices, life support products or other critical applications. inclus ion of cirrus products in such applica- tions is understood to be fully at th e customer's risk and cirrus disclaims a nd makes no warranty, express, statutory or implied, including the implied warranti es of merchantability and fitness for particular purpose, with regard to any cirrus product that is used in such a manner. if the custome r or customer's customer uses or permits the use of cirrus products in critical applications, customer agrees, by such us e, to fully indemnify cirrus, its officers, directors, em- ployees, distributors and other agents from any and all liabi lity, including attorn eys' fees and costs, that may result from or arise in connec tion with these uses. cirrus logic, cirrus, and the cirrus logic logo designs are trad emarks of cirrus logic, inc. all other brand and product names in this document may be trade- marks or service marks of their respective owners. spi is a trademark of motorola, inc.

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